Responsibilities: Working with all partners such as lead architects and block design teams to understand features to be implemented and verified. Robust testplan for both synthetic testing and real workload trace Debug verification test failures, working with the design team to accurate defects Make sure AMD next generation GFXIP can meet performance/power/function expectation Requirements: Must have Min 5 years of experienced in ASIC verification. Must be proficient in Verilog and System Verilog language Must be good at C/C++ programming, and working in Linux and Windows environments Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and do test plan, test creation and triage, coverage and assertion etc. Be proficient of script language like Perl, Python Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail Must have good English hearing, speaking, reading and writing capabilities Must have good teamwork and interpersonal skills Graphics pipeline experience is preferred Deep knowledge of computer architecture is preferred Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering with Digital Systems/VLSI as major with 5+ Years of Exp
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