Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Verification ( SV , UVM ) (2-4 Years) (Bangalore)

Greetings!

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world.

Looking for passionate Verification professional If, interested kindly send your CV along with Current CTC & Notice period & CV to

Have a position to offer at Cadence Design Systems, Bangalore

Work location: Bangalore

Experience : 2 - 4 Years

Education : M.E./MTech (Electronics or similar) or B.E/BTech. (Electronics or similar)

JD

: Verification ( SV / UVM ) Solutions Engineer

In this role, you will work on a team which is defining a high throughput metric driven simulation-based regression environment. The responsibilities include setting up, running, analyzing, and optimizing simulation-based regression environments and working with R&D teams to define requirements for how to improve an Xcelium-based simulation regression flow running on a local server farm as well as a cloud server farm.

Job Requirements:

• Bachelor's Degree in Electrical or Computer Science Engineering
• xperience in design and/or verification of complex digital designs, or Applications engineering/technical support role.
• Strong background on functional verification fundamentals
• System Verilog UVM constrained-random testbench experience
• Understanding of load sharing software like LSF
• Experience with Cadence Xcelium/Incisive Simulator, and vManager - Advantage
• Experience with Cloud - Advantage
• Excellent communication skills. Must have ability to communicate complex issues to internal teams and customers in a clear and concise manner.
• Strong debug skills for diagnosing issues
• Proficiency in Unix/Linux scripting languages (ksh / csh / python / perl / etc...)
• Some travel may be required

Unfeigned Regards

K Madhu Prasad (Madhu Reddy)
Hiring Team

We're doing work that matters. Help us solve what others can't.