Syntiant Corp., a leader in the high-growth AI software and semiconductor solutions space, is looking for an experienced and talented
SoC Design Engineer
.
The
SoC Design Engineer
will be responsible for developing Syntiant's next generation Neural Decision Processor SoCs. The ideal candidate will be a self-starter who can execute all design cycle tasks from architecture to tapeout as well as silicon bring-up and validation while working with cross-disciplinary teams (Design, Firmware, Product, OPS & Field Engineering).
Specific Duties and Responsibilities:
Microarchitecture and implementation of SoC design blocks
Integrate and verify design blocks at chip level
Quality checks of the implemented RTL with LINT, CDC and DFT rules with clear documentation of exceptions and waivers
Synthesis, constraints and timing closure for the SoC
Logic Equivalence Check (LEC) for SoC design blocks and for the full SoC
Implement low power modes for the SoC using UPF
Implement Design-for-Test (DFT) features in the SoC
Participate in silicon bring-up, validation and characterization
Provide quality documentation of the implementation and other deliverables with systematic reviews.
Work with OPS team to resolve volume manufacturing issues
Work with cross functional teams to debug and resolve platform and customer issues
Requirements
Qualifications, Education, and Experience Required:
Advanced degree in electrical engineering or computer engineering
Track record of 'first-pass success' in ASIC development cycles
6+ years of experience with SoC development using SystemVeilog/Systemc
Expertise in SoC and Subsystem design of ARM based SoCs
Deep understanding of Synthesis, constraint development and timing closure
Deep understanding of design quality checks (Lint, CDC, DFT rules)
Experience with Low Power Design using UPF
Experience with scripting languages, e.g. Python
Experience with High Level Synthesis (HLS) using SystemC is a big plus
Experience with silicon bring up and debug as well as developing chip demo
Experience with SoC performance analysis is a plus
Knowledge of ARM architecture and AMBA bus standards like AXI, AHB & APB
Knowledge of Design for Test (DFT) features and implementation is a plus
Knowledge of SoC power estimation flow is a plus
Benefits
About Syntiant:
Founded in 2017 and headquartered in Irvine, Calif., Syntiant Corp. is a leader in delivering hardware and software solutions for edge AI deployment. The company's purpose-built silicon and hardware-agnostic models are being deployed globally to power edge AI speech, audio, sensor and vision applications across a wide range of consumer and industrial use cases, from earbuds to automobiles. Syntiant's advanced chip solutions merge deep learning with semiconductor design to produce ultra-low-power, high performance, deep neural network processors. Syntiant also provides compute-efficient software solutions with proprietary model architectures that enable world-leading inference speed and minimized memory footprint across a broad range of processors. The company is backed by several of the world's leading strategic and financial investors including Intel Capital, Microsoft's M12, Applied Ventures, Bosch Ventures, the Amazon Alexa Fund, and Atlantic Bridge Capital. More information on the company can be found by visiting www.syntiant.com.
One element in our total compensation package is base pay. Individual compensation decisions are based on a number of factors, including but not limited to previous experience and skills acquired prior to joining Syntiant, cost of living in the assigned work location, assigned schedule, and salaries of similarly situated peers at the company. It is to be expected that candidates will come to us with different sets of skills and experiences and therefore will be paid at different points in the stated range. We recognize that the person(s) we select for hire may be less experienced or more experienced than the role as posted; if this is the case, any updates to available salary ranges will be communicated with candidates during the recruitment process.
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