Job Description

Job Title: SoC Design Engineer (ARM / RTL / Integration)
Experience: 6 10 Years
Location: Hyderabad / Bengaluru, India
Employment Type: Full-Time
Domain: Semiconductor | ASIC | AI SoC Design About the Role
We are looking for a highly motivated SoC Design Engineer with strong front-end ASIC design expertise to support the development of next-generation AI SoCs. This role focuses on microarchitecture, RTL development, subsystem integration, and ARM-based platform design.
The ideal candidate will bring hands-on experience in SoC design (not verification-only roles) and strong exposure to ARM architecture, AMBA protocols, and ASIC design methodologies. Key Responsibilities
Design and integrate ARM-based subsystems derived from Arm Corestone or similar reference platforms.
Develop and modify RTL for CPU subsystems, interconnect fabrics, memory controllers, and peripheral IP.
Drive SoC/IP integration activities including subsystem bring-up and design optimization.
Collaborate with architecture teams on microarchitecture definition, performance tuning, and feature implementation.
Work closely with verification teams to debug functional issues and achieve coverage closure.
Support synthesis, timing closure, and physical design during SoC execution.
Perform design quality checks including lint, CDC, RDC, LEC, and STA analysis.
Contribute to low-power design methodology and design scalability improvements.
Participate in documentation, design reviews, and early silicon/emulation bring-up. Core Technical Skills Required
Hiring managers will prioritize candidates with strong hands-on SoC Design experience covering: Front-End ASIC Design
Microarchitecture development
RTL coding (SystemVerilog/Verilog)
SoC Integration / IP Integration
ASIC Synthesis & Design Flow Design Methodology & Sign-off
Clock Domain Crossing (CDC)
Reset Domain Crossing (RDC)
Lint & Logical Equivalence Check (LEC)
Static Timing Analysis (STA)
Low Power Design & UPF concepts Architecture & Protocols
ARM Architecture (Corestone experience preferred)
AMBA protocols: AXI, AHB, APB
Peripheral interfaces: I2C, SPI Additional Technical Exposure
Debugging across simulation, synthesis, and timing environments
FPGA prototyping or early silicon bring-up (preferred) Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
6 10 years of hands-on experience in SoC or subsystem design.
Strong experience in RTL design, SoC integration, and front-end ASIC methodologies.
Proven background in ARM-based SoC development and AMBA interconnect architecture. Preferred Qualifications
Exposure to AI/ML accelerator-based SoCs.
Experience with low-power design techniques and clock/power domain architecture.
Familiarity with Cadence/Synopsys tools for synthesis, STA, CDC, and low-power analysis.
Programming knowledge in C/C++, Perl, or scripting languages is a plus. Soft Skills
Strong analytical and debugging capability
Excellent collaboration across architecture, PD, and verification teams
Ability to work in a fast-paced silicon development environment Why Join?
Work on next-generation AI silicon and advanced SoC platforms
Collaborate with world-class architecture and design teams
Opportunity to influence scalable SoC solutions from concept to silicon
#LI-AS1

Skills Required