DFT pattern generation, fault simulation, and coverage analysis
.
Work closely with DFT and verification teams to improve test coverage and quality.
Debug ATPG patterns and support silicon bring-up and test activities.
Optimize test methodologies to enhance efficiency and reduce test time.
Required Skills
Strong hands-on experience in
SoC-level ATPG
and fault coverage improvement.
Proficiency in
DFT tools
such as Synopsys TetraMAX, Cadence Modus, or equivalent.
Good understanding of
DFT architectures
-- scan insertion, MBIST, JTAG, boundary scan.
Familiarity with
STA, synthesis, and RTL design flows
.
* Excellent problem-solving and debugging skills.
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