Job Description

SMTS - ASIC Security Design Verification Engineer

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Hyderabad, India Engineering 56869

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SMTS SILICON DESIGN ENGINEER

Lead ASIC Security Design Verification Engineer

Position Overview

We are seeking a Lead ASIC Security Design Verification Engineer to drive verification strategy and lead a team of engineers. The role involves architecting verification environments, mentoring team members, and ensuring robust security implementations in complex ASIC designs.

Essential Responsibilities

Lead and manage a team of design verification engineers Define and drive verification methodology and strategy for security-focused ASIC projects Architect advanced verification environments using UVM methodology Review and approve verification plans, test scenarios, and coverage metrics Guide technical decisions for verification infrastructure and framework development Establish best practices for security verification across projects Drive cross-functional collaboration with design, software, and product teams Provide technical leadership in verification reviews and project meetings Mentor and develop team members' technical and professional growth

Required Qualifications

Bachelor's degree in Engineering, Information Systems, Computer Science, or related field 10+ years of Hardware Engineering experience with at least 5 years in lead verification roles Proven track record of leading complex verification projects and teams Expert-level knowledge in RTL design verification using Verilog/System Verilog/UVM methodology In-depth understanding of security protocols and cryptographic implementations: + Symmetric and asymmetric cryptography
+ Public/private key infrastructure
+ Hash functions and random number generators
+ Encryption/signature algorithms (AES, SHA, GMAC)
+ Inline cryptography

Advanced programming skills in Verilog, C/C++, Python, and Perl Strong experience in verification planning and coverage-driven verification Exceptional problem-solving and debugging skills Outstanding leadership and communication abilities

Preferred Qualifications

Master's degree in Electrical Engineering Experience leading security-critical tape-outs Expertise in hardware security architecture and threat modeling Knowledge of formal verification methodologies Experience with verification IP development and reuse strategies Track record of implementing verification process improvements Publications or patents in hardware security or verification

Leadership Competencies

Proven ability to build and lead high-performing technical teams Excellence in project planning and execution Strong decision-making and problem-solving abilities Effective stakeholder management skills Ability to mentor and develop team members Strategic thinking and innovation mindset

Technical Leadership

Establish verification standards and methodologies Drive adoption of new verification technologies and tools Lead technical reviews and design discussions Guide architectural decisions for verification environments Contribute to organizational verification strategy


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