Job Description

Minimum qualifications: Bachelor\'s degree in Electrical Engineering, Computer Science engineering, or equivalent practical experience. 3 years of experience in silicon validation. Experience programming in C and Python. Experience in developing silicon validation tests and debugging post-silicon issues. Preferred qualifications: Master\'s degree or PhD in a related domain. Experience with embedded software development, related toolchains, and hardware debugging tools (e.g., JTAG, TRACE32, etc.) Experience with Android, Embedded Linux, RTOSes, or bare metal platforms. Experience in test automation or system level testing (SLT). About the job Our computational challenges are so unique we can\'t just purchase off-the-shelf hardware, we\'ve got to make it ourselves. Your team designs and builds the hardware, software, and networking technologies that power all of Google\'s services. As a Hardware Engineer, you design and build the systems that are the heart of the world\'s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. With your technical expertise, you lead projects in multiple areas of expertise (e.g., engineering domains or systems) within a data center facility, including construction and equipment installation, troubleshooting, or debugging with vendors. Google\'s mission is to organize the world\'s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people\'s lives better through technology. Responsibilities Perform SLT planning, test development, test stabilization, and debugging to support the silicon volume ramp at the system level. Collaborate with Design and Validation leads to support the SLT platform. Collaborate with internal test engineers, partner engineers, and contract manufacturers on screening parts, and sign off on the SLT releases. Collect the post-silicon data to improve the production quality and yield.

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