Job Description

We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.

AMD together we advance_

AMD is currently looking for a dynamic individual to work within IPSE (IP and System Engineering) Group on the next-generation MPSOC FPGA design. The individual will manage and contribute to the architecture and implementation of the verification test bench using System Verilog and UVM. This individual will work closely with designers to develop a testplan and a stand-alone methodology that is easily portable and reusable within the system testbench. The individual needs to work with teams who are in different geographical areas.

Responsibilities include the definition of the verification methodology and the testbench architecture, review of the verification specs, cover groups and test plans, development of constraint-random stimulus generators, bus-functional models, scoreboards, etc.

Qualifications

• BS/MS EE, CE, or CS
• 4+ years of design verification experience
• 3+ years of OOP coding experience (VERA, System Verilog, SpecmanE or C++) and SV Assertions
• Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM
• Familiarity with Verilog and General Logic Design concepts
• Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR4/DDR5, and peripherals such as USB and Ethernet
• Strong working knowledge of UNIX environment and scripting languages such as Perl or Python
• Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim
• Experience using UNIX Revision Control tools - Subversion, RCS, CVS, Perforce and bug tracking tools such as Bugzilla
• Experience in verifying multimillion gate chip designs from specifications to tape-out
• Excellent communication and presentation skills
• Demonstrate the ability to work with cross-functional teams
• Familiarity with processors and boot flow would be useful
• Familiarity with Software development flow including assembly and C is beneficial