Job Description

This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products.

Your Role

Key responsibilities in your new role:

This role will empower you to

lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products.

Architect and develop test benches and environments.

You will create, simulate, and debug test scenarios, and lead regressions and issue tracking.

There will be collaboration with design and systems engineering teams to review specifications and architecture,extract features, and define verification plans.

You'll drive coverage analysis and closure, and collaborate with /support digital + mixed-signal co-simulations

using System Verilog analog behavioral models. Working closely with Analog team and AMS simulation and verification.

Define verification plan and verification architecture required for verifying required RTL.

Execute Defined test-plans to ensure bug free tapeout. Develop required verification components. Test plan execution and debugging of RTL. Meet verification targets (coverage closure, Regression clean-up). AMS verification will involve extensive testing of top level AMSsimulation ( RTL + Spice).

Your Profile

Qualifications and skills to help you succeed:

Bachelors/Master's degree in Electronics /Electrical Engineering 10+ years of Industry experience Digital DV + Leadership experience verifying complex IP with a track record of

robust ASICs.

+ Advanced knowledge of ASIC verification flows with

System Verilog and UVM.

+ Experience developing test benches from scratch, bringing up designs in simulation.
+ Skills with constrained random testing, coverage closure, and RTL /gate simulations.
+ Proficient in a scripting language such as Python, Perl, Bash orsimilar.
Great teammate / mentor with excellent communication skills and the desire to seek diverse challenges. Exposure to AMS verification is a Plus and would be given preference + Understanding of RTL + Spice simulation
+ Willingness to learn basics of analog design
+ Familarity with VerilogA and other modeling should be help
+ Basic Analog concepts like KCL, KVL etc.
+ Exposure to

AC2DC or DC2DC

products is a great advantage
+ Willingness to work with analog team for top level AMS verification.
Exposure to cocotb based verification is an added preference.

Contact:

swati.gupta@infineon.com

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