Job Description

Drive the optimization and strategy for SoC Chip Development from architecture through Front end RTL, DFT, physical implementation (Rtl2Gds) and chip verification. Ensuring learnings and improvements across multiple platform products aligns with the various Chip Development disciplines . Owning key decisions for the global optimization while keeping business imperatives in mind.

In your new role you will be:

Driving optimization and the charter of SoC Chip development from architecture through Front end RTL, DFT, physical implementation (Rtl2Gds) and chip verification. Driving the SOC Platform strategy and leading teams across multiple locations . Ensure learnings and improvements across multiple platform products. Align various Chip Development disciplines and be responsible for key decisions for global optimization while keeping business imperatives in mind.

Your Profile

You are best equipped for this task if you have:

Overall of 18+ years of experience as a Chip design expert Experience as 10 Years chip lead and a chip architect for consumer products like IOT, mobile, processors etc with focus on low power. Experience working in any of the Finfet technologies. Expertise in using and optimising Industry Standard Methodologies for RTL2GDS, DFT and Functional verification domains. Hands on experience in using the state of the art suite of tools from Mentor, Synopsys and Cadence. Experience on developing chips from planar to finfet taking into account Power, Performance & Area optimization triangle. Experience working cross cultures and driving topics across regions

Contact:

Hains.Henrita@infineon.com

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