Job Description

Title: Senior Member of Technical Staff - SOC Architect

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit

Introduction

The engineer will be responsible for driving SOC level tech leadership, customer facing, working with cross functions/teams/geo, stakeholders.

Job Responsibilities:

Need to have spent significant time & Expertise on at least one of the domains in SOC.

To achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation.

These candidates will create Power Intent for the designs and verify power intent on RTL, run static Low-Power checks on gate level netlists, Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates, setup signoff Static Timing Analysis and ECO flows and achieve timing closure Working with the Design/DFT/PD teams, run Power Analysis and estimate power at RTL level, run Sign off Power Analysis on the P&R data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows.

Experience with Synopsys tools for ASIC Synthesis and Timing Constraints and DFT implementation that includes MBIST and Scan Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks. Experience with Verilog and System Verilog RTL design experience with Perl/TCL/Makefile scripting Experience with Power Analysis using Power Artist and PTPX Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows

Execute block-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure.

Need experience in full chip physical design such as integration of blocks, top level floorplanning, clock tree synthesis, timing constraints development and convergence. I/O placement and constraints. Experience with UPF coding and modification as per design requirements. Need to take care of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.

Expected to interact with the global product and test engineering teams.

Experience with owning chip level DFT architecture, execution and Post Silicon debug / analysis Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification.

Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Experience with automotive SOCs (field test, advanced fault models,..) is an advantage.

Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis.

In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis In depth knowledge and hands on experience in MBIST insertion and Memory test validation Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.

Experience in RTL and Gate level simulations of scan and MBIST test vectors Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax) Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus

Required skills and Qualification

• Bachelor or Master's degree in Electrical and Electronics engineering.
• Auto FuSA is preferred. Experience in RTL coding in system verilog is strongly preferred. Understanding of IC design with Analog circuits and it's design cycles is an added advantage.
• Effective communication skills to interact with all stakeholders. Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies.
• Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills Excellent communication and team work skills and good English is required.
• The candidate should have good people skills to work closely with the systems, analog, layout and test team Must be highly focused and remain committed to obtaining closure on project goals.
• Good understanding of low power concepts. Good exposure in Floorplanning, CTS, STA, Physical Verification.
• Good understanding of top-level physical design, partitioning and timing constraints, IR Drop. Basic understanding of timing constraints. Knowledge in Automation script (TCL, Perl, etc), Auto FuSA would be an added advantage.

GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

To ensure that we maintain a safe and healthy workplace for our GlobalFoundries employees, please note that offered candidates who have applied for jobs in Singapore will have to be fully vaccinated prior to their targeted start date. For new hires, the appointment is contingent upon the provision of a copy of their COVID-19 vaccination document, subject to any written request for medical or religious accommodation.

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