Job Description

Job Requirements

Role:

Senior Design Verification Engineer (VLSI)

Experience:

~4 years

Key Responsibilities:

Write and execute test plans for digital IP/SoC verification. Develop testbenches using SystemVerilog/UVM. Run simulations, debug failures, and ensure design quality. Work with design and architecture teams to close verification gaps. Contribute to coverage, regressions, and automation scripts.

Skills Required:

SystemVerilog, UVM, simulation tools (VCS/Questa/Incisive). Good understanding of digital design, RTL, and verification methodology. Strong debug and problem-solving skills. Exposure to scripting (Perl/Python/TCL) is a plus.

Work Experience

Skills Required:

SystemVerilog, UVM, simulation tools (VCS/Questa/Incisive). Good understanding of digital design, RTL, and verification methodology. Strong debug and problem-solving skills. * Exposure to scripting (Perl/Python/TCL) is a plus.