Job Description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows.
What You Can Expect

• Design, implement, and maintain large-scale HPC clusters for EDA workloads, ensuring high availability, fault tolerance, and efficient resource utilization.
• Manage, configure, and optimize LSF job scheduling systems to support diverse verification workflows.
• Develop, automate, and monitor deployment, configuration, and operational processes for EDA infrastructure.
• Collaborate with EDA engineers and designers to refine verification flows to run optimally on the grid.
• Implement and advance CI/CD pipelines to streamline the deployment, testing, and monitoring of infrastructure and EDA flows.
• Provide troubleshooting and support for users and the infrastructure.
• Monitor infrastructure health, performance, and usage; proactively identify, resolve, and document issues.
• Ensure compliance with security best practices, license management, and data protection requirements.
• Contribute to architectural innovation and process improvement for future scalability and efficiency.
• Participate in incident management teams for prompt issue resolution.

What We're Looking For

• Bachelor's or Master's degree in Computer Science, Electrical Engineering, or related field. 2-4 yrs of industry experience.

Proficiency with Programming or scripting in languages such as Python, Bash, or Perl for automation and workflow development.

• Working knowledge of Linux system administration and cluster troubleshooting.

Familiarity with infrastructure-as-code, configuration management, and monitoring , DevOps and SRE concepts

• Strong communication and collaboration skills; ability to work in cross-functional teams.
• Track record of identifying and implementing infrastructure optimizations for efficiency, throughput, and reliability.

Preferred Qualifications:

• Experience with cloud-based EDA infrastructure or hybrid HPC environments.
• Familiarity with regression management tools, and workflow automation specific to silicon verification.
• Experience with HPC cluster management, especially using LSF/Platform LSF, in a chip verification or EDA context.

Key Attributes:

• Analytical, detail-oriented, and proactive in identifying and solving technical problems.
• Passion for continuous learning and embracing new technologies and methods.
• Strong organizational abilities and commitment to documentation and process improvement.

This role is essential in ensuring that our chip verification teams have a robust, high-performance, and adaptable infrastructure to accelerate silicon innovation.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
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