Job Description

About Blaize

About Blaize

Blaize is building a hybrid AI platform engineered to support edge-to-cloud intelligence at scale--delivering efficient, scalable AI designed for complex, multimodal workloads across industries. We serve critical infrastructure sectors including smart city, defense, retail, manufacturing, healthcare, and automotive.
Our full-stack programmable processor architecture and low-code/no-code software platform enable real-time AI processing for high-performance computing at the network's edge and in the data center. Blaize solutions deliver actionable insights with low power consumption, high efficiency, minimal size, and low cost.
Headquartered in El Dorado Hills (CA), Blaize has over 200 employees worldwide, with teams in San Jose (CA) and Cary (NC), and subsidiaries in Hyderabad (India), Leeds and Kings Langley (UK), and Abu Dhabi (UAE).
To learn more, visit www.blaize.com or follow us on LinkedIn at @blaizeinc.

DESCRIPTION

We work on complex high performance, fully programmable, low power design of

Graph Streaming Processor

, an architecture specially designed for machine learning/visual applications. As a member of our focused group of HW engineering, the candidate will be involved in designing a stream processor and memory subsystem working on every aspect of hardware design and will be involved in close interactions with both SDK and backend teams for performance tuning, area, and power optimizations of multi million gate design.

EDUCATION AND EXPERIENCE

BE/BTech/ME/MTech in Computer Science or Electronics or Electrical 5-7 years of experience

REQUIRED KNOWLEDGE, SKILLS, AND ABILITIES

Capability to understand a given block specification and come up with Micro Architecture Capability to derive architecture and micro architecture based on a given algorithm Experience in processor design - RISC/DSP/VLIW/SIMD architectures and/or memory subsystem design, cache hierarchy design. Knowledge in digital logic for HW safety/protection - ECC, Parity, WDT etc. Experience of multi-million gate ASIC design and verification methodologies Good understanding of Computer Architecture, ISA, Caches and Memory Hierarchy. Experience in performance and power analysis of processor-based systems. Experience in AMBA AXI, AHB, and APB protocols Knowledge of digital design methodologies and tool flow Excellent logic design, debugging and problem-solving skills. Experience in logic design with Verilog and/or System Verilog and validation/verification Experience in lint checks, area optimization, power optimization, GLS, synthesis and timing analysis Experience in Multi-clock domain, Interconnects Knowledge on Memory subsystem Knowledge in Automotive ISO 26262 Functional Safety Standard is a plus. Experience with DSP, Datapath design and floating-point math a plus Understanding of GPU/AI/ML Processor architecture Blaize is an equal opportunity employer. We pride ourselves on having a diverse workforce and we do not discriminate against any employee or applicant because of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition, or any other basis protected by law. We respect the gender, gender identity, and gender expression of our applicants and employees, and we honour requests for preferred pronouns. It is our policy to comply with all applicable national, state, and local laws pertaining to non-discrimination and equal opportunity.