Job Description

Summary Description:
Syntiant Corp., a leader in the high-growth AI software and semiconductor solutions space, is looking for an experienced and talented Senior ASIC Design Engineer to take on a critical role with expansive responsibilities to enhance the Hardware Engineering function in a growing organization.
As Digital ASIC Design Engineer, you will be a key player in the ASIC R&D team. You are presented with a unique opportunity to be part of the complete digital ASIC design flow, from specification and modelling, implementation and verification, to synthesis and silicon bring-up. Further, you will play an important role in supporting complex failure analyses to ensure smooth ramp-ups and high-volume production.
Specific Duties and Responsibilities:

• Architect & implement Syntiant's next-generation Neural Digital Processor (NDP) for low-power edge AI applications.
• Work closely with Machine Learning (ML) team to analyze, map & co-optimize state-of-the-art neural network models to Syntiant's current and next-generation NDP engine.
• Create power and performance profiling tool for NDP engine.
• Lead PPA (Power/Performance/Area) tradeoff analysis to improve design.
• Pre-/post-silicon design validation and performance testing.

Requirements
Qualifications, Education, and Experience Required:

• Minimum Masters degree in electrical engineering with 5+ yrs industry experience, PhD preferred with + 3 yrs experience.
• A proven track record of 5+ years in developing low-power signal processing IPs from architecture to implementation.
• Open to candidates with varied backgrounds, including a PhD with 0-1 year of experience or a Master's with 3 years of experience. Final level of role will align with the candidate's education and experience.
• Hands-on experience developing IPs using SystemC HLS (High-Level Synthesis).
• Good knowledge and experience in architecture/design of NPUs.
• Good knowledge in ML network architecture (Dense, CNN, RNN, Transformer, etc).
• RTL implementation of Digital Signal Processing algorithms, using Verilog or System Verilog.
• Implementation of test benches and digital verification methods.
• Experience in PPA (Power/Performance/Area) optimizations.
• Programming/scripting languages (e.g., Python, C/C++, or Perl).
• Task centered, self-driven, persistent, and team oriented.
• Experience with ML frameworks (Tensorflow, PyTorch, etc.) is a plus.

Benefits
About Syntiant:
Founded in 2017 and headquartered in Irvine, Calif., Syntiant Corp. is a leader in delivering hardware and software solutions for edge AI deployment. The company's purpose-built silicon and hardware-agnostic models are being deployed globally to power edge AI speech, audio, sensor and vision applications across a wide range of consumer and industrial use cases, from earbuds to automobiles. Syntiant's advanced chip solutions merge deep learning with semiconductor design to produce ultra-low-power, high performance, deep neural network processors. Syntiant also provides compute-efficient software solutions with proprietary model architectures that enable world-leading inference speed and minimized memory footprint across a broad range of processors. The company is backed by several of the world's leading strategic and financial investors including Intel Capital, Microsoft's M12, Applied Ventures, Bosch Ventures, the Amazon Alexa Fund, and Atlantic Bridge Capital. More information on the company can be found by visiting .
One element in our total compensation package is base pay. Individual compensation decisions are based on a number of factors, including but not limited to previous experience and skills acquired prior to joining Syntiant, cost of living in the assigned work location, assigned schedule, and salaries of similarly situated peers at the company. It is to be expected that candidates will come to us with different sets of skills and experiences and therefore will be paid at different points in the stated range. We recognize that the person(s) we select for hire may be less experienced or more experienced than the role as posted; if this is the case, any updates to available salary ranges will be communicated with candidates during the recruitment process.

Skills Required