Job Description

Job Requirements

Understanding the RTL design and Uarch of IPs and integrating them in sub-systems SoC IP Uarch definition and RTL development Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc. Design for Testability (DFT) checks Low Power Checks RTL Synthesis and STA support Pre and Post Silicon functional verification support Close collaboration with different domain teams DDR knowledge

Work Experience

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6-10 years of IP/SoC Design Experience Experience is SoC design and integration for complex SoCs is a must. Experience in Synthesis / Understanding of timing concepts is a plus. Should have knowledge of AMBA protocols - AXI, AHB, APB besides SoC clocking/reset architecture. Strong RTL design and coding experience in Verilog, system Verilog, VHDL etc. * Experience with micro-architecture and design of digital IPs and subsystems