Job Description

Overview:

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences--from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges--striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

Responsibilities:

RTL DESIGN ENGINEER

THE ROLE

:

We are looking for a Senior Silicon Design Engineer to design and deliver low?power SoC design programs.
The role spans SOC design, support for simulation, GLS, X?prop analysis, STA sign?off, Power optimization support across complex subsystems.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

+

IP Integration

and related tasks in collaboration with IP vendor, RTL , Verification PD and FW teams. +

Champion design quality

: lint/CDC/DFT readiness, regressions, bug triage, and issue closure across Synopsys flows (synthesis, formal, simulation).
+

Partner on timing closure (STA) across corners

: own sign?off criteria for blocks/subsystems.
+

Develop Timing Constraints

-Being able to code, understand Timing Constraints for DC/PT is a plus
+

Support Verification

for functional, Gate?Level Simulation (GLS) and X?propagation analysis to drive clean resets and convergence for SOC
+

Document learnings and publish best

?

practice guides

to reduce cycle time and improve first?time?right outcomes. (Quality/systemization responsibility common to Sr. roles.)
+

Design and Debug

Independently with minimum guidance, on new SOC blocks/subsystems

PREFERRED EXPERIENCE:

6+ years

of SoC/Silicon design experience, with emphasis on

low

?

power design

,

power intent (UPF)

,

clock/reset

,

CDC

,

SOC design,IP Integrations

The candidate should be proficient in microarchitecture development from system level architecture document Should have done SoC level integration of IO peripheral protocols (example SDIO/eMMC, USB, Ethernet etc.) Hands?on proficiency with

Synopsys toolchain

(e.g.,

Design Compiler

,

PrimeTime/STA

,

VCS

/

Verdi

) and scripting (

Python

,

TCL

,

Shell

). Demonstrated success leading

GLS/X

?

prop

efforts and cross?functional

readiness reviews

to closure Strong ownership, communication, and collaboration skills across RTL/PD/FW/test teams Experience with

ARM/SNPS IPs

is a plus

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering


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Qualifications:
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.