TITILE: RTL DESIGN ENGINEER (Principal/Senior Staff/Staff Engineer)
Location: Bangalore/Hyderabad
EXPERIENCE: 10 years to 15 years
RTL design in Verilog/SystemVerilog
-Micro-architecture, integration & debug
-Synthesis-friendly coding practices
-Experience in ASIC SoC designs
ROLES AND RESPONSIBILITIES:
-RTL design in Verilog/SystemVerilog
-Micro-architecture, integration & debug
-Synthesis-friendly coding practices
-Experience in ASIC SoC designs
MNCJobsIndia.com will not be responsible for any payment made to a third-party. All Terms of Use are applicable.