Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Product Validation Engineer II

Location: Noida

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world\xe2\x80\x99s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence\xe2\x80\x99s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique \xe2\x80\x9cOne Cadence \xe2\x80\x93 One Team\xe2\x80\x9d culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other\xe2\x80\x94every day.

Job Summary

This position requires the development of RTL design, Verification IPs and environment for functional verification

• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must
• System Verilog experience and experience with UVM based functional verification environment development is required
• Prior RTL Design experience using Verilog/System Verilog is a must
• Prior experience in IP development would be an added advantage
• Developing test suite and compliance test suite for 100% functional coverage for a given specification.
• Interaction with R&D and PE and resolving issues in a timely manner.
• Development of scripts for automations using Python and Perl

Job Responsibilities

• Good working knowledge of various verification concepts such as Verification architecture, coverage, checkers, test plan etc.
• Knowledge of Verification environments based on UVM, System Verilog
• Programming skills: Verilog, System Verilog mandatory. C/C++ would be a plus.
• To work closely with Product Engineers and R&D on understanding customer design requirements
• Develop test plans and write tests based on the requirements
• Execute on test plans and perform unit, integration, solutions level validation
• Very good debugging and analytical skills
• Should have good communication skills and should be a good team player

Qualifications

• BE/BTech/ME/MS/MTech in Electrical/Electronics

Experience and Technical Skills required

• 2+ years of experience in Verification

• Expertise in one or more domains \xe2\x80\x93 UVM, System Verilog

Behavioral skills required

• Must possess strong written, verbal and presentation skills
• Ability to establish a close working relationship with both R&D and PE teams
• Explore what\xe2\x80\x99s possible to get the job done, including creative use of unconventional solutions
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity

Regards

K Madhu Prasad (Madhu Reddy)
Hiring Team

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We\xe2\x80\x99re doing work that matters. Help us solve what others can\xe2\x80\x99t.

Cadence Design Systems