Principal Verification Engineer – Soc/ip Design & Verification

Year    TS, IN, India

Job Description

Job Summary




We are seeking a

Principal Verification Engineer

to lead the functional verification of complex SoCs and IP blocks for next-generation high-performance computing (HPC), AI acceleration, and data center products. The ideal candidate will have deep experience in

SoC/IP functional verification

,

UVM/SystemVerilog

, and

coverage-driven methodologies

, with a strong focus on ensuring first-pass silicon success.


In this leadership role, you will drive

end-to-end verification strategy

, collaborate cross-functionally with architecture and design teams, and influence product definition through early design engagement.

Experience in Virtual Modeling, SystemC, and TLM

is a

strong plus

, enabling advanced verification flows and early software co-development.

Key Responsibilities



Verification Planning & Execution

+ Own the definition and implementation of

IP and SoC-level verification plans

, including test strategy, coverage goals, and schedule.
+ Develop

UVM/SystemVerilog-based

testbenches for complex IP and SoC subsystems, focusing on scalability, reuse, and maintainability.
+ Lead

coverage closure

activities, including functional, code, and formal coverage, to ensure comprehensive verification.

Cross-Functional Collaboration

+ Work closely with

RTL designers, architects, firmware/software teams

, and post-silicon validation to align on requirements and drive co-verification strategies.
+ Participate in

architecture and microarchitecture reviews

, providing verification insights and influencing design for testability and verification efficiency.

Debug & Root Cause Analysis

+ Perform advanced

debug and root cause analysis

of complex functional issues, collaborating with cross-disciplinary teams to drive resolutions.
+ Utilize industry-standard tools for

waveform analysis, simulation debug, and emulation/prototyping platforms

.

Methodology & Process Improvement

+ Define and drive best practices in

verification methodology

, including constrained-random testing, assertion-based verification, and coverage-driven approaches.
+ Contribute to

automation and regression flows

, optimizing for quality and turnaround time.

Technical Leadership & Mentorship

+ Mentor junior verification engineers, guide technical reviews, and contribute to team development and growth.
+ Champion a culture of

technical excellence, innovation, and continuous improvement

.



Qualifications

Required Qualifications



Education & Experience

+ B.S./M.S. in Electrical Engineering, Computer Engineering, or related discipline.
+

10+ years of hands-on experience

in IP and/or SoC verification with a track record of successful silicon products.

Technical Expertise

+ Proven expertise in

UVM/SystemVerilog

for developing scalable, reusable verification environments.
+ Strong understanding of

complex SoC designs

, including

memory controllers (DDR5, HBM3), PCIe, CXL

, and high-speed interfaces.
+ Experience with

coverage-driven verification

and closure techniques (functional, code, assertion coverage).
+ Solid background in

debugging RTL issues

, simulation-based testing, and interaction with emulation/FPGA prototyping teams.

Verification Tools & Languages

+ Proficient in

simulation tools

(VCS, Questa, Xcelium),

waveform viewers

, and scripting languages (

Python, Perl, TCL

) for automation.
+ Familiarity with

formal verification tools

and techniques is a plus.



Additional Information

Preferred/Additional Skills



Virtual Modeling and System-Level Verification

+ Experience with

SystemC

and

Transaction-Level Modeling (TLM)

for creating virtual platforms and enabling early software/hardware co-verification.
+ Knowledge of

Virtual Prototype (VP) development

for system-level validation and performance modeling.

Pre-silicon Software Co-verification

+ Exposure to

software-hardware integration

, including early firmware/driver bring-up on virtual or emulated environments.

Low-Power Verification

+ Familiarity with

power-aware verification methodologies

(UPF/CPF) and power intent validation.

Leadership in Verification Strategy

+ Experience driving

complex multi-IP and SoC-level verification

efforts, including coordination with global teams.



Renesas is an embedded semiconductor solution provider driven by its Purpose '

To Make Our Lives Easier

.' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.



With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, '

To Make Our Lives Easier

.'



At Renesas, you can:

Launch and advance your career

in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.

Make a real impact

by developing innovative products and solutions to meet our global customers' evolving needs and help make people's lives easier, safe and secure.

Maximize your performance and wellbeing

in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.

Are you ready to own your success and make your mark?


Join Renesas. Let's

Shape the Future

together.


Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

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Job Detail

  • Job Id
    JD3850034
  • Industry
    Not mentioned
  • Total Positions
    1
  • Job Type:
    Full Time
  • Salary:
    Not mentioned
  • Employment Status
    Permanent
  • Job Location
    TS, IN, India
  • Education
    Not mentioned
  • Experience
    Year