Eteros Technologies Inc. provides worldwide semiconductor customers and professionals with a suite of solutions from design realization to talent management and custom AI/ML solutions. Our vision is to become an essential and integral part of our customer's product and talent development roadmaps through our offerings.
Lead the DFT implementation of a complex SoCs
Work hands-on critical tasks as and when needed
Own the DFT implementation flows, methodologies, and execution of SoCs??Experience in all phases of the DFT pre- and post-Si for large SoCs
??Implement DFT of SoC/Full-chip-level and/or high-speed cores/blocks
??Experience in high-speed, low-power, mixed-signal SoC's is a plus
??Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries
??Experience in developing DFT architecture, Test-plan, implementation methodologies
??Experience in scan insertion, memory-BIST, JTAG/IJTAG, CTL, IEEE 1149.1/1500 wrappers, BSCAN,
Compression, ATPG, Simulations, post-Si testing/debug
??Experience in manual test-point insertion, improve coverage targets, high-compression
??Experience in hierarchical ATPG, OCC/OPCG, power-aware scan/ATPG methodologies
??Experience in test-mode constraints generation and test-mode timing closure
??Experience in patter generation for foundry, post-Si support/debug
??Thorough understanding of digital design, timing analysis, and physical design process
??EDA Tools: Synopsys (DFTC, Tetramax, TestMax-DFT, SMS, PTSI)
Requirements
??Experience should be 12+ years
?? Proven track record with multiple successful final production tape outs
??Proven ability to independently deliver results in a very fast-moving startup environment, be able to work hands-on as and when needed
??Be able to work under limited supervision and take complete accountability.
Excellent written and verbal communication skills
Benefits
What's in it for you:
Work on leading edge technologies
An opportunity for career development and growth
Competitive compensation
Exceptional benefits
I'm interested
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