Job Description

Principal Architect - Isolated Gate Driv...LNT/PA-IGDI/1545580


LTST-L&T Semiconductor Technologies LimitedBengaluru
Posted On
04 Nov 2025
End Date
03 May 2026
Required Experience
10 - 15 Years

Skills
Knowledge & Posting Location


ELECTRONICS


Minimum Qualification


DIPLOMA IN ELECTRONICS ENGINEERING

Principal Architect - Isolated Gate Driver IC

Areas of Responsibilities Lead architecture and design definition for isolated gate driver ICs used with SiC and GaN power switches, optimized for high switching speed, high CMTI, and robustness. Architect complete driver solutions including: High/low side output stages (with Miller clamp, active pull-up/down, configurable source/sink) Isolation interface (capacitive, magnetic, or optical) Integrated protections (UVLO, DESAT, SCP, soft turn-off, active clamp) Diagnostic and telemetry features (SPI/IC interface, status flags) Define system-level integration strategy for energy platforms, ensuring reliable performance across wide operating voltages, temperatures, and transient conditions. Ensure design meets isolation standards (UL1577, VDE0884, IEC 60747-17) and supports high CMTI (>100 kV/s) performance. Collaborate with SiC/GaN FET designers, power module architects, and system teams to define drive strength, layout constraints, and thermal performance targets. Guide the team on HV layout practices, creepage/clearance, EMI reduction, and packaging co-design. Drive IP reuse, design scalability, and enable the gate driver IP to be leveraged across energy, automotive, and industrial portfolios. Lead architecture reviews, mentoring, and documentation of system specifications and design decisions. Contribute to long-term roadmap and technology strategy for wide-bandgap driver solutions across all business units

Technical Skills:

Expert in gate driver circuit design for wide-bandgap devices (SiC MOSFETs, GaN HEMTs). Strong understanding of: Level shifters, push-pull buffers, active clamps, and short-circuit protection Isolation technologies and barrier design (capacitive/magnetic/optical) High-side/low-side driver pairing and bootstrap techniques Experience with protection and diagnostics: UVLO, DESAT, OCP, OTP, and integrated fault reporting. Knowledge of high-voltage (>600 V) and high-frequency (>100 kHz-1 MHz) design constraints. Tools: Cadence Virtuoso, Spectre, MATLAB, and simulation tools (e.g., PLECS, ADS, LTspice). System-level co-design experience with SiC/GaN switches, power modules, and packaged solutions.

Strong foundation in EMI/EMC, thermal behavior, and safe operating area (SOA) management