InCore is a leading processor design company with a strong focus on innovation and customer success. Our vision is to be a global leader in processor design, empowering customers with groundbreaking RISC-V-based solutions. We are driven by our mission to harness the power and flexibility of RISC-V architecture and deliver unparalleled performance and efficiency through comprehensive solutions. Our values of innovation, collaboration, quality, adaptability, and customer success guide our approach as we reimagine the way processors and SoCs are designed and manufactured.
At InCore, we pride ourselves on fostering a dynamic and inclusive work environment that encourages creativity, collaboration, and professional growth. Our team of experts works closely together in a supportive and open atmosphere, where diverse perspectives and ideas are valued. We believe in nurturing talent and providing ample opportunities for career advancement, continuous learning, and skill development. Please visit incoresemi.com to know more about InCore.
We are seeking a motivated and technically skilled intern (2 positions) to lead the transformation of our existing RISC-V Application Profiler into a comprehensive trace analysis suite equivalent to ARM's Tarmac Trace Utilities. This role combines systems programming, performance analysis, and benchmark development to create next-generation profiling tools for RISC-V processors.
Key Responsibilities
Phase 1 (4-6 months): RISC-V Profiler Enhancement
Add interactive trace browsing capabilities
Develop function call tree analysis
Create multiple output formats (flame graphs, histograms, etc)
Phase 2 (3-4 months): Microbenchmark Framework
Build automated benchmark decomposition tools
On-board new benchmark suits into our existing CI/CD framework
Extract microbenchmarks from standard suites (CoreMark, SPEC CPU, etc)
Develop pattern recognition for performance-critical code
Create validation framework
Phase 3 (1-2 months): Integration & Testing
Comprehensive testing and documentation
Performance validation
Enhanced RISC-V profiler with ARM Tarmac-equivalent features
50+ validated microbenchmarks from standard benchmark suites
Automated benchmark decomposition framework
Complete documentation and user guides
Requirements
Enrolled in / recently graduated from a Bachelor's, Master's or PhD program in Computer Engineering, Computer Science, Electrical Engineering, or a related technical discipline.
Strong programming fundamentals in C/C++ and Python.
Strong RISC-V fundamentals and Computer Architecture.
Ability to work 30-40 hours per week for a minimum of 24-weeks, 36-48 weeks preferable.
Benefits
This role offers unique exposure to the growing RISC-V ecosystem and potential for full-time conversion based on performance.
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