Overview:
Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Layout Design to join our MIC Design IDC team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.
As a PE Layout Design, you'll be owning the chip level collaterals. In this full-time role, you'll report directly to our layout manager. Our MIC design team is dedicated to develop and cater the industry-leading memory interface chips and your contributions will be instrumental in achieving this goal.
Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.
Responsibilities:
Responsible for layout deliverables for the assigned project, would be leading the layout team.
Strong fundamental knowledge in Cadence virtuoso XL/VXL features, and layout verification checks LVS, DRC, Antenna, and Density with Calibre is a must.
Working with cross-functional teams across globe and collaboration with designers to solve layout issues.
Floorplan, powergrid and signal planning and reviews.
Expertise in bump-out planning, die area estimation and related problem solving.
Experience in fixing various reliability issues EMIR, EOS, ESD/Latchup.
Expertise in standard layout practices such as Layout matching, parasitic, noise & noise isolation, supply consideration, latch up, shielding, Well's substrates and Isolation.
Qualifications:
Degree in Electrical/Electronic Engineering or equivalent with 12 to 15 years of relevant experience.
Experience in layout design of Transmitter, receiver, PLL, clocking, PI, Bandgap and voltage regulators would be an added benefit.
They should have layout experience in 22nm, FINFET nodes 16nm, 12nm, 7nm.
Sound knowledge of double patterning, device matching, signal shielding, layout parasitic and layout dependent effects.
Strong fundamental knowledge in semiconductor device physics, cross-section, and construction.
Knowledge of skill/Perl/tcl scripting is desirable.
Should be a good team player and self-motivated.
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