PDT & FM Lead (Physical Design Tools & Flow Methodology)
Location:
Bangalore, Karnataka
Experience:
7 - 18 Years
Budget:
Up to 30 LPA (Depending on Experience)
Industry:
Semiconductors | AI | Networking | ASIC Design
Job Overview
We are looking for a highly skilled
Physical Design Tools & Flow Methodology (PDT & FM) Lead
to drive the development, optimization, and deployment of robust design flows and methodologies for advanced semiconductor design. The ideal candidate will have deep expertise in EDA tools, scripting automation, and physical design methodologies across cutting-edge technology nodes. This role combines
technical leadership, innovation, and vendor engagement
, making it key to the success of next-generation ASIC and AI-driven solutions.
Key Responsibilities
Flow Development & Automation:
Design, develop, and maintain scalable and automated physical design flows for synthesis, floorplanning, placement, CTS, routing, and sign-off verification.
Tool Evaluation & Benchmarking:
Lead evaluation, benchmarking, and deployment of industry-leading EDA tools (Synopsys, Cadence, Mentor) to ensure state-of-the-art methodologies.
Methodology Enhancement:
Continuously identify and resolve bottlenecks in existing flows; implement innovative methodologies to improve
PPA (Power, Performance, Area)
and reduce
TAT (Turn-Around Time)
.
Technical Leadership:
Act as a subject matter expert (SME) for physical design teams; provide hands-on support for flow usage, tool issues, and complex design closure challenges.
Vendor Collaboration:
Partner with EDA vendors to resolve tool bugs, drive feature enhancements, and influence product roadmaps aligned with project needs.
Documentation & Training:
Develop detailed documentation of flows, scripts, and methodologies; conduct training to upskill internal design teams.
Process Node Enablement:
Drive flow enablement for advanced process technologies (7nm/5nm and below), including creation of design rules, methodologies, and foundry-compliant automation.
Key Skills
Synthesis & PnR Expertise:
Proficiency in Synopsys Fusion Compiler/ICC2 and/or Cadence Innovus/Genus.
Sign-Off Tools Mastery:
Strong experience with PrimeTime, Calibre/ICV, RedHawk/Voltus, Totem, and related tools.
Floorplanning & Power Grid:
Strong expertise in floorplanning principles and
power grid mesh creation/analysis
.
Scripting & Automation:
Expert-level proficiency in
TCL
; advanced scripting skills in
Python/Perl
for automation.
Advanced Nodes:
Proven experience working with advanced nodes (7nm/5nm and below).
Problem-Solving:
Exceptional debugging and analytical skills; able to resolve complex design challenges independently.
Collaboration & Mentorship:
Strong communication skills; ability to mentor junior engineers and collaborate with global, cross-functional teams.
Preferred Qualifications
Master's or PhD in
Electrical Engineering, Computer Engineering, or related field
.
Track record of contributions to
flow innovation
and
design methodology improvements
in product-based semiconductor companies.
Job Types: Full-time, Permanent
Pay: ₹1,000,000.00 - ₹3,000,000.00 per year
Benefits:
Health insurance
Provident Fund
Education:
Master's (Required)
Work Location: In person
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