Job Description

NXP Semiconductors N.V. (NASDAQ: NXPI) is the world leader in secure connectivity and processing solutions for embedded applications. NXP is solving the world\xe2\x80\x99s most complex technology challenges to accelerate business innovation, enhance how we work, and advance how we live.

Design Enablement PDK(Process Design Kit) Team is responsible for providing Best In Class PDKs for NXP Product/IP design teams. PDK Team has a global footprint across different geographical regions \xe2\x80\x93 Asia Pacific, Europe and America regions. As a PDK engineer the candidate will work with Foundry, NXP Technology Team, Modelling Team, Reliability Team and other partner teams to create differentiating PDKs for NXP Design Community. Candidate will be part of a global team working together to enable the best, unique and differentiating solutions for NXP design community by partnering with Foundry and EDA partners and thereby improving design efficiency and reduced cycle time.

Scope of Responsibilities

• Development of Calibre physical verification decks for cmos FinFET, bulk, SOI, RF, bicmos and powermos technologies including DRC, LVS, PERC, Fill LPE, and shape generation decks and scripts.
• Development of parasitic and EMIR rule decks for cmos FinFET, bulk, SOI, RF, bicmos and powermos technologies including interface development for LVS, LPE and SNA decks and scripts.
• Development and validation of PV tools and flows like parasitic extraction, EMIR drop and substrate noise analysis.
• Development of the Process Design Kit (PDK) infrastructure for PV tools, flows and utilities which includes setups, configurations, integration of technology specific data.
• Responsibilities will include testing, validation, customer support and new tool/methods evaluations, development of methods and procedures for quality improvement, automation of deck/techFiles generation and validation.

• Requires 8+ years of experience with development and support of (1) Physical verification rule decks/runsets - DRC/LVS/ERC/PERC/FILL Or (2) Parasitic and EMIR rule decks
• In depth knowledge of foundry based and EDA tools based process variation formats e.g. ICT, IRCX etc. and understands latest EMIR & EM challenges.
• Experience with either - Calibre SVRF/TVF rule deck coding OR Cadence PVS/Assura rule deck coding is a must.
• Experience with some of the following tools is required: Calibre, CalibreXRC, Assura, Assura RF, Cadence PVS, Synopsys ICV, Virtuoso, Cadence QRC, StarRCXT, Voltus, Redhawk.
• Experience with at least 2 of the following programming languages is a plus: perl, python, skill, shell, c/c++, tcl.

• BE/B.Tech/ME/M.Tech in Electrical or Electronics Engineering or other similar discipline with at least 8 years of relevant experience

NXP Semiconductors