Job Description

Job Requirements

Job Requirements

Minimum qualifications:

Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.



6+ year of experience with physical design.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.



Experience with scripting languages such as Perl, Python, or Tcl.



Experience with constraints, synthesis or clock tree synthesis (CTS).



Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in ASIC design.

Responsibilities:

Participate in the physical design of blocks for TPU chips.



Contribute to the design and closure of the subchip and individual blocks from RTL-to-GDS.



Collaborate with RTL/Design and physical design (PD) teams to achieve the best power/performance/area (PPA) possible. Conduct feasibility studies for new microarchitectures as well as optimizing runs for best quality of result (QoR).