Job Description

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We Are Hiring - Multiple DFT Positions (4-10 Years)

Location: Bangalore

Employment Type

Full-TimeWe are expanding our VLSI DFT Engineering team in Bangalore and looking for talented professionals across multiple experience levels. If you have strong expertise in Scan, ATPG, MBIST, IJTAG, Hard IP, JTAG, Boundary Scan, BIST, or Repair Flows, we want to connect with you!

Open PositionsDFT Engineers (4-6 Years)

DFT Engineer - Scan Insertion & ATPG2

DFT Engineer - MBIST & IJTAG3

DFT Engineer - Hard IP & JTAGSenior DFT Engineers (6-8 Years)

Senior DFT Engineer - Scan & ATPG5

Senior DFT Engineer - MBIST & BIST (Clocking)

Senior DFT Engineer - Hard IP & Boundary ScanLead DFT Engineers (8-10 Years)

Lead DFT Engineer - Scan & ATPG

Lead DFT Engineer - MBIST & Repair Flow

Lead DFT Engineer - JTAG & Hard IP Testing

Key Skills
RequiredScan Insertion, ATPG, Test CompressionMBIST, BIST, Memory Test AlgorithmsIJTAG (IEEE 1687), JTAG (IEEE 1149.x)Hard IP DFT, Boundary ScanRepair Flow (BIRA/BISR)Scripting: Python / Perl / TCLExpertise with Synopsys / Cadence / Mentor DFT tools
Responsibilities
(Role-Dependent)Develop and implement DFT architecture at IP, Subsystem & SoC levels.Insert Scan/ATPG/MBIST/JTAG logic and ensure test rule compliance.Generate ATPG patterns and drive coverage closure.Debug GLS, MBIST, scan-chain, and silicon bring-up issues.Collaborate with RTL, PD, STA, Test, and Validation teams.Lead and mentor junior engineers for senior/lead positions.
Share your CV:
daniinfogine@gmail.com
9985155421

Job Type: Full-time

Pay: ₹1,000,000.00 - ₹4,000,000.00 per year

Work Location: In person