Job Description

MTS SILICON DESIGN ENGINEER

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Bangalore, India Engineering 63082

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WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

MTS SILICON DESIGN ENGINEER ( SOC Low Power-RTL lead)

THE ROLE:

As a member of the Client Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

The Person:

If you have a knack for power saving techniques, including clock gating and UPF-based power gating, this role is for you. You will be responsible for generating Power spec, UPF, performing quality checks of power-gated digital designs, execute the SoC RTL integration and working collaboratively with the IP team.

Key Responsibilities:

Understanding of IP/SS/SoC Power Management(PM) techniques. Converting PM Specification to UPF Perform low power quality checks VSI/VCLP Debugging experience on Power aware simulation (NLP sim) Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including UPF, verification, Power sequence, and post-silicon bring-up Need to understand clocking, reset and soc top level topology changes to make connectivity as per the topology across Ips. Need to understand the requirements of power domain(power architecture) to write UPFs. Collaborate with architects, DV and PD engineers to understand the new features to group the logic into tiles based on functionality as well as PD FP requirements. Must have been expert with RTL coding and other Debug capabilities.

Preferred Experience:

7+ years full-time experience in IP/SOC hardware design Experience doing ECOs Experience with power aware CDC runs Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Experience with RTL Quality Checks - Verilog lint tools (Spyglass), verilog simulation tools (VCS) and Clock domain crossing (CDC) tools Proficient in IP level ASIC or SoC level RTL integration work and verification Good understanding and hands-on experience in the Timing, UPF, CDC, RDC and other quality check concepts Proficient in debugging RTL code using quality check and simulation tools. Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills Exposure to leadership or mentorship is an asset.

ACADEMIC CREDENTIALS:Bachelors or Masters degree in computer engineering/Electrical Engineering


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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.