Job Description

Architect and implement digital ASIC designs meeting performance, power, and area

requirements.

? Develop and execute verification plans using industry-standard methodologies such as UVM

(Universal Verification Methodology).

? Write and debug RTL (Register Transfer Level) code in Verilog/SystemVerilog.

? Create and maintain verification environments, including testbenches, models, and functional

coverage.

? Collaborate with cross-functional teams including physical design, software, and validation to

ensure successful tape-out.

? Analyze and debug simulation failures and work closely with design teams to resolve issues.

? Participate in design reviews, providing feedback and guidance to improve design quality and

efficiency.

? Stay current with industry trends and advancements in ASIC design and verification

methodologies.

Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field.

? Solid understanding of digital design fundamentals and ASIC design flow.

? Proficiency in Verilog/SystemVerilog and experience with ASIC design tools Synopsys).

? Familiarity with verification methodologies such as UVM and scripting languages (e.g., Perl,

Python).

? Experience with FPGA prototyping and emulation platforms is a plus.

? Strong analytical and problem-solving skills.

? Excellent communication and teamwork abilities.

? Ability to thrive in a fast-paced, dynamic environment.

Job Type: Full-time

Pay: ₹862.91 - ?1,362.74 per day

Work Location: In person