to join our semiconductor design team in Bangalore. The candidate will be responsible for developing
memory compilers and high-performance cache instances
for next-generation cores, ensuring optimal
Power, Performance, and Area (PPA)
outcomes.
Key Responsibilities:
Design, develop, and validate
SRAM/memory compilers
and
Fast Cache
instances.
Conduct circuit-level simulations, optimizations, and quality checks for memory margins and characterization.
Analyze PPA trade-offs and implement design improvements for performance and efficiency.
Collaborate with cross-functional teams on architecture, timing, and layout integration.
Perform circuit simulations and debugging using EDA tools from
Cadence
and
Synopsys
.
Document design methodologies, verification procedures, and design reviews.
Required Skills & Experience:
Bachelor's or Master's degree in
Electronics, Electrical, or VLSI Engineering
.
Minimum
2+ years of experience
in
SRAM/memory design
, characterization, and margin analysis.
Strong understanding of
CMOS transistor behavior
,
high-speed/low-power circuit design
, and
clocking schemes
.
Knowledge of
Static and Complex Logic Circuits
and
PPA trade-offs
.
Proficiency in
circuit simulation and optimization
.
Good interpersonal and communication skills.
Nice to Have:
Experience with
Perl, TCL, or Python
scripting.
Exposure to
Cadence or Synopsys design flows
.
Familiarity with
standard cell design and circuit-level optimization
.
Job Types: Full-time, Permanent
Work Location: In person
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