Eteros Technologies Inc. provides worldwide semiconductor customers and professionals with a suite of solutions from design realization to talent management and custom AI/ML solutions. Our vision is to become an essential and integral part of our customer's product and talent development roadmaps through our offerings.
Summary:
Good understanding of timing concepts, a good understanding of SDC and constraints syntax, and experience in Timing Analysis both at block level and SoC level.
You must have experience with Industry Timing sign off tools like Prime time / Tempus, DMSA or Tweaker, and MMMC
As a Static Timing Analysis Engineer, you will work with the design and implementation teams to develop and qualify timing constraints, solve timing challenges in Block/SOC by manually closing difficult paths, and work closely with the physical design engineers to resolve implementation-related timing issues.
You should also have a clear understanding of Cross-talk delay/noise, Timing derates, AOCV/POCV concepts, and its impact on design closure.
In addition, you should have experience in Timing & Noise Sign-off Closure at block level or Full chip-level on advanced process nodes, be able to plan and track self-execution, and report results on a regular basis systematically. Hands-on scripting skills on TCL / Perl are a must.
Requirements
Qualifications:
BTech/MTech/PhD with 6-8 years' experience in STA
Proven track record with multiple successful final production tape-outs
Be able to work under limited supervision and take complete accountability.
Excellent written and verbal communication skills
Benefits
Benefits:
Work on leading edge technologies
An opportunity for career development and growth
Competitive compensation
Exceptional benefits
I'm interested
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