Lead Engineer Memory Layout

Year    KA, IN, India

Job Description

Job Requirements



Hands-on experience with SRAM, register files, ROM, TCAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc.


Should have worked on at least 7nm Finfet process technologies. 6nm, 5nm, 4nm,3nm will be an added advantage .


Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the Memory.


Good hold on IR/EM related issues in memory layouts.

Work Experience



Hands-on experience with SRAM, register files, ROM, TCAM layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc.


Should have worked on at least 7nm Finfet process technologies. 6nm, 5nm, 4nm,3nm will be an added advantage .


Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the Memory.


Good hold on IR/EM related issues in memory layouts.

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Job Detail

  • Job Id
    JD4096875
  • Industry
    Not mentioned
  • Total Positions
    1
  • Job Type:
    Full Time
  • Salary:
    Not mentioned
  • Employment Status
    Permanent
  • Job Location
    KA, IN, India
  • Education
    Not mentioned
  • Experience
    Year