Job Description

Job Title: Lead DFT Engineer
Location: Bengaluru
Experience: 12+ Years
Notice Period: 30days
Role Overview
We are seeking an experienced Lead DFT Engineer to drive the integration and optimization of Design-for-Test (DFT) architecture in our LiDAR SoCs. In this role, you will own DFT strategy, planning, implementation, and validation across our high-performance silicon platforms.
Key Responsibilities

• Define, develop, and implement DFT methodologies for high-performance LiDAR SoCs.

• Own DFT planning, insertion, verification, and validation processes.

• Collaborate with RTL Design, Physical Design, and ASIC vendors to ensure robust test implementation for automotive-grade SoCs.

• Partner with IP vendors to ensure proper DFT integration at the SoC level.

• Support post-silicon bring-up, debug, silicon failure analysis, and yield improvement activities.

• Create and maintain DFT documentation, guidelines, and test architecture specifications.

What You'll Bring

• 12+ years of experience in DFT architecture and test strategy development for complex ASIC/SoC designs.

• Strong expertise in industry-standard and proprietary DFT techniques, including:

• SCAN/ATPG

• Built-in-Self-Test (MBIST/LBIST)

• JTAG (IEEE 1149.x/1500/1687)

• Boundary Scan (BSCAN)

• Compression/Decompression technologies for Digital & Mixed-Signal SoCs

• Hands-on experience with EDA tools (Mentor, Synopsys, etc.).

• Proficiency in scripting languages such as Python, PERL, TCL.

• Solid knowledge of RTL coding and SDC creation for DFT modes.

• Proven tapeout experience in advanced semiconductor nodes.

Nice to Have

• Familiarity with developing automotive-grade silicon meeting AEC-Q100 qualification.

• Experience working under ISO 26262 functional safety standards.

Skills Required