Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The role requires working with the existing functional verification environment, addition of new features into the verification environment or creating completely new verification environment from scratch and ensuring various customer configurations are clean meeting required DV metrics. Sometimes there may also be need to support customers in case of any issues with design. Participate in Technical alignment with verification expert in Defining verification strategy, architecting verification environment. Also interface with other domains such as RTL , Physical design, Analog design and modelling teams. Technically small team/project depending on the project requriements. Contribute towards Defining, developing and deploying new functional verification methodologies. The engineers should have strong background in functional verification fundamentals, verification environment planning & development, test plan creation. Prior Digital verification experience in some of the serial bus multiprotocol PHY IP\'s (such as SerDes, USB/DPHY,UCIe) is expected. Other verification domain skills: -Strong expertise in Verilog, HVL( SV , e) with UVM methodology -Experience in assertions development/closure, constraint randomization, functional coverage, code coverage. -Strong RTL and GLS debug skills. Expertise in more than two of following skills is desirable and added plus: -Power-aware RTL set-up, simulation and debug -Formal verification. -Gate-level simulations. -Good to have ( not must have ): Some experience or understanding and usage of Analog models. Basic awareness of mixed-mode simulations with Analog/digital,-Some exposure to Automotive IP verification (fault injection), emulationexposure though not mandatory but good to have. We\'re doing work that matters. Help us solve what others can\'t.

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