Job Description

Job Summary (List Format):
- Responsible for design and development of critical analog, mixed-signal, custom digital blocks, and full chip-level integration.
- Expertise required in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
- Perform layout verification (LVS, DRC, Antenna checks), quality checks, and support documentation.
- Ensure on-time delivery of block-level layouts with high quality.
- Utilize excellent problem-solving skills for physical verification of custom layouts.
- Accurately execute tasks to meet project schedules and milestones in a multi-project environment.
- Guide and review junior team members' sub block-level layouts, especially on critical items.
- Contribute to effective project management activities.
- Communicate effectively with local engineering teams to ensure project success.
- Requires BE or MTech in Electronics/VLSI Engineering.
- Minimum 5 years experience in analog/custom layout design in advanced CMOS process (TSMC 3nm/5nm/7nm experience preferred).
- TSMC certification required.

Skills Required