Job Description

ob Description: IP Verification / Formal Verification Engineer

Location:

Bangalore (Only local candidates)

Availability:

Immediate to Short Notice Only

Opening 1: IP Verification Engineer

Experience:

10+ Years

Role Overview

We are looking for a senior

IP Verification Engineer

with strong hands-on experience in microarchitecture, RTL development, and IP design for multimedia applications.

Key Responsibilities

Develop

micro-architecture

from design requirements and define

HW-SW interfaces

. Work closely with design teams on

RTL development and IP integration

. Verify and validate complex IP blocks for

video and audio subsystems

. Ensure protocol compliance and performance optimization.
Required Skills & Qualifications

10+ years of hands-on experience in

microarchitecture and RTL development

. Strong proficiency in developing

micro-architecture from design requirements

. Solid experience in defining

hardware-software interfaces

. In-depth understanding of

MIPI CSI and DSI protocols

. Experience designing and verifying

IP blocks for video and audio

applications.
Opening 2: Formal Verification Engineer

Experience:

5+ Years

Role Overview

We are seeking an experienced

Formal Verification Engineer

with deep expertise in formal methodologies and strong debugging skills.

Key Responsibilities

Perform

Formal Verification

of complex RTL designs using industry-standard tools. Develop and review

SystemVerilog assertions

and formal test strategies. Analyze and debug formal failures using trace, trigger, and debug techniques. Collaborate with design and verification teams to close coverage and correctness gaps.
Required Skills & Qualifications

5+ years of experience in

Formal Verification

.

Expert-level experience with JasperGold

(mandatory). Strong expertise in

SystemVerilog

and

UVM

(mandatory). Experience in

debug, trace, and trigger analysis

is a strong plus.
Job Type: Permanent

Pay: ₹2,000,000.00 - ₹5,000,000.00 per year

Work Location: In person