Job Description

The Foundation Design IP group (FDIP) is responsible for the Design Kit Solutions, Logic Libraries, SRAM/ROM embedded memories and IO/ESD libraries within NXP.
We deliver competitive and qualified Foundation IP as part of a Design Platform Package to accelerate BU productivity and growth. We have built, and continue to build, deep insight into the basic component requirements and architectural challenges of electronic system solutions in automotive and security & connectivity applications.

Job Summary: This vacancy is for IO group which is growing in size in Bangalore and being the major player for all the BLs and product lines.

7+years of Work experience in deep sub-micron technologies, Finfet, and FDSOI technology
Very Good understanding of the local layout effects in the lower technologies
Hands-on layout experience in GPIO, IIC Auxiliary cells, High-speed IOs like LVDS, I2C etc.
Prepare layout floor-plan and review it with the designer
Understanding of EMIR, Latch-up, ESD strategy, power planning, quality check (QC)
Ability to plan and work independently and coordinate with cross-functional teams

Chip level experience of IO Layout and verification

Mandatory Skills:

Should be IO layout domain with experience in top level ring creation, Floor planning till final GDS verification

Cadence tool experience ,calibre and PVS, EM analysis

ESD knowhow and Challenges in Deep sub-micron

Preferred Skills:

Automation using SKILL, PERL/Python and Shell scripting

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status.