Are you ready to join the pioneering team at PierSight Space? We're a Space-Tech company with teams in Ahmedabad, California and Bangalore on a mission to build the world's largest constellation of Synthetic Aperture Radar and AIS satellites for comprehensive ocean surveillance. With backing from prestigious institutional investors like Alphawave Global, Elevation Capital, All in Capital, and Techstars, we're set to make a significant impact.
Key Responsibilities:
2-4 years of hands-on experience in implementing designs on FPGA
Strong expertise in RTL coding of complex designs using Verilog/SV
Expertise in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure
Early architectural/performance exploration through micro-architectural definition and design
Optimize the design to meet power, performance, area and timing requirements
Run unit level testing to deliver quality code to the Design Verification Team
Create well written block level design documentation
Write testbench and sequences in SystemVerilog.
Familiarity with lab equipment
Familiarity with interface protocols (PCIE, Ethernet)
Knowledge of latest FPGA architectures and partitioning designs across multiple FPGAs
Exposure to scripting languages
Preferred Experience:
Hands on experience with FPGA design suite Libero
Tcl/perl/python scripting languages
Good hardware and software debugging skills
Experience running quality checks such as CDC
Experience in synthesis, static timing analysis
Experience with verification and UVM is added advantage.
* Experience with FPGA Hardware design is added advantage
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