Job Description

Location Hyderabad
Experience Range 5 - 6 Years

Job Title:FPGA Design Engineer


:oStrong in digital design.

Strong in Xilinx Vivado IP & IPI tools till bit-generation. Knowledge of VHDL/Verilog/System Verilog. Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up. Proficiency in Linux environment. Good communication skills.

Basic Job Deliverable:RTL coding, IP design, Modify/update existing IP as per requirements.


Qualification:Bachelor's/Master's in ECE


Experience Level: 5+ Years


Hiring Manager:


Expected hire date:ASAP


Pay Scale pm:As per standard


Expected hire duration:6 month to 1 years , may extend depending on the project & need


To be placed on Xilinx Hyderabad location :Xilinx Hyderabad


Note: This position required to work at AMD Hyderabad Office