Job Description

Project Role :

Formal Verification Engineer

Project Role Description :

Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.

Must have skills :

SoC Verification

Good to have skills :

NA

Minimum

3

year(s) of experience is required

Educational Qualification :

15 years full time education



Summary: We are seeking a highly skilled Senior Digital Verification Engineer with a minimum of four years of experience in UVM-based digital verification. The ideal candidate will have expertise in verifying AMBA protocols and core IPs, including DMA architectures with high throughput and complex descriptor structures. Candidates with a Master's degree from top Indian institutions (IIT, NIT, IIIT - top 20) are strongly preferred. Applicants should document their State entrance rank and GATE percentile as part of their qualifications. Roles & Responsibilities: o Develop and execute UVM-based verification environments for digital IPs, focusing on AMBA protocols and DMA engines. o Design and implement testbenches to thoroughly verify complex descriptor structures such as linked lists and scatter/gather mechanisms. o Analyze and debug verification failures, ensuring robust coverage and compliance with functional requirements. o Collaborate with architecture, design, and firmware teams to define verification strategies and resolve issues. o Document verification plans, test cases, and results; maintain clear and organized reporting. o Contribute to the continuous improvement of verification methodologies and best practices. Professional & Technical Skills: o Minimum 4 years of hands-on experience in UVM digital verification. o Strong background in AMBA protocols (AXI, AHB, APB) and core IP verification. o Expertise in verifying DMA architectures capable of 5Gbps throughput. o Proficient in handling complex data structures, including linked lists and scatter/gather descriptors. o Solid understanding of digital design concepts, RTL, and simulation tools. o Familiarity with scripting languages (e.g., Python, Perl) for automation and debugging. o Excellent problem-solving and analytical skills. Additional Information: o Master's degree from IIT, NIT, IIIT (top 20 schools in India) is mandatory. o Candidates must provide documentation of their State entrance rank and GATE percentile. o Strong communication skills and ability to work effectively in a team-oriented environment. o Prior experience in a fast-paced semiconductor or IP development environment is an advantage.




15 years full time education