Job Description

Job Requirements

Microarchitecture, Module design and simulation Participate in SoC specifications reviews and contribute to micro-architecture definitions. Digital design, implementation, and integration - RTL Coding, Lint, CDC, and Synthesis. Develop design constraints and coordinate to debug both functional and DFT test issues. Synthesis and P&R constraint generation, including clock tree specification Scan insertion and pattern generation Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support for timely closure of assigned blocks design and implementation issues. Work with Product, Test, and Applications Engineering to complete product release B.A./B.S. in engineering, engineering management, or engineering operations required BSc/BEng in Electrical or Electronic engineering, MS preferred

5-7 years

industry experience with BS working in digital or mixed signal IC design Digital design knowledge: + Verilog coding
+ Register file design
+ Serial interfaces
+ Interconnect fabrics
+ State machine architecture
+ Clock domain crossing
+ Scan and self-test
+ Synthesis, Linting, STA
+ Automation scripting and design flows
+ Verification, including System Verilog knowledge
+ Low power design, Power intent specification and validation methodology.
System knowledge: + Battery management, charging, voltage regulation and ARM based Subsystems/SOCs.
Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation,Lint, CDC/RDC and power intent checks. Familiarity with Cadence, Synopsis design tools Ability to work as part of a team and with low levels of supervision Good understanding of customer and market requirements Microarchitecture, Module design and simulation Participate in SoC specifications reviews and contribute to micro-architecture definitions. Digital design, implementation, and integration - RTL Coding, Lint, CDC, and Synthesis. Develop design constraints and coordinate to debug both functional and DFT test issues. Synthesis and P&R constraint generation, including clock tree specification Scan insertion and pattern generation Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support for timely closure of assigned blocks design and implementation issues. Work with Product, Test, and Applications Engineering to complete product release

Work Experience

B.A./B.S. in engineering, engineering management, or engineering operations required BSc/BEng in Electrical or Electronic engineering, MS preferred

5-7 years

industry experience with BS working in digital or mixed signal IC design Digital design knowledge: + Verilog coding
+ Register file design
+ Serial interfaces
+ Interconnect fabrics
+ State machine architecture
+ Clock domain crossing
+ Scan and self-test
+ Synthesis, Linting, STA
+ Automation scripting and design flows
+ Verification, including System Verilog knowledge
+ Low power design, Power intent specification and validation methodology.
System knowledge: + Battery management, charging, voltage regulation and ARM based Subsystems/SOCs.
Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation,Lint, CDC/RDC and power intent checks. Familiarity with Cadence, Synopsis design tools Ability to work as part of a team and with low levels of supervision * Good understanding of customer and market requirements