Job Description

Design IPs or Hierarchical blocks solutions for high-performance and low-power applications, collaborating with cross-functional teams to define project requirements. Conduct feasibility studies and censuring alignment with project goals and objectives. Enable Place and route ,clock tree synthesis capabilities for the SoC Integration. Implement and optimize digital designs using hardware description languages (HDLs) like Verilog or VHDL, considering design trade-offs and performance metrics. Evaluate RTL coding, timing analysis, synthesis, and functional verification to ensure the correctness and robustness of the design. Pead and participate in verification efforts, including writing testbenches, running simulations, and debugging functional and timing issues. Collaborate with physical design engineers to guide and optimize the layout to performance and power targets. 2 to 5 years of relevant work experience in RTL to GDS Experience in physical design, timing closure, and physical integration/signoff. Should have multiple tape-out experiences. Proficiency in industry standard RTL development/ analysis and synthesis tools. A drive to continuously learn and expand architectural breadth and depth. Ability to evaluate microarchitectural options for tradeoffs across design, verification, and PD. Experience interconnecting and analyzing complex microarchitectural structures and subsystems. Proven experience in IPs or Hierarchical blocks design, ideally with a focus on complex digital systems and high-performance computing. Proficiency in hardware description languages (HDLs) such as Verilog or VHDL, and familiarity with EDA tools for synthesis and verification. Strong understanding of design methodologies, including RTL coding, functional verification, and timing closure. Familiarity with scripting languages (e.g., Python, Perl) for automating design tasks is a plus. Excellent problem-solving and analytical skills, with a keen attention to detail. Ability to work effectively in a team-oriented and fast-paced environment. Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development. Effective communication and interpersonal skills, with the ability to collaborate with cross-functional teams. BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.