Job Description

Job Requirements

Responsibilities:

Verification Planning & Strategy:

+ Develop detailed verification plans based on architectural specifications and functional requirements for CPU designs.
+ Define verification methodologies and strategies, including testbench architecture and coverage metrics.
+ Identify critical verification scenarios and edge cases.

Testbench Development:

+ Architect and implement highly robust and scalable verification environments using UVM (Universal Verification Methodology).
+ Develop complex test sequences, constrained random tests, and directed tests to achieve comprehensive coverage.
+ Create reusable verification components (e.g., UVM agents, sequencers, drivers, monitors, scoreboards).
+ Develop assertions (SVA) to monitor design behavior and detect violations.

Verification Execution & Debug:

+ Execute verification plans on simulators (e.g., Cadence Xcelium, Synopsys VCS, Mentor QuestaSim).
+ Debug complex functional and performance issues, identifying root causes in RTL (Verilog) and collaborating with design teams for resolution.
+ Analyze coverage data (code, functional, assertion) and drive towards verification closure.
+ Develop and maintain regression suites.

Collaboration & Improvement:

+ Work closely with RTL design engineers, architects, and software teams to understand design intent and verification requirements.
+ Contribute to the continuous improvement of verification methodologies, flows, and tools.
+ Participate in design and verification reviews.

Minimum Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 3+ years of experience in digital IC verification. Strong proficiency in Verilog and SystemVerilog. Extensive hands-on experience with UVM for building complex testbenches. Solid understanding of CPU architecture concepts (e.g., pipelining, cache coherence, memory management units, instruction sets). Experience with industry-standard simulation tools. Proficiency in scripting languages (e.g., Python, Perl, Tcl) for automation and data analysis. Excellent problem-solving, analytical, and debugging skills. Strong written and verbal communication skills.

Preferred Qualifications:

Experience with ARM CPU architecture and instruction sets (e.g., ARM Cortex-A, Cortex-R, Cortex-M series).

Experience with formal verification techniques (e.g., assertion-based verification, model checking). Familiarity with emulation and FPGA prototyping for pre-silicon validation. Knowledge of low-power verification techniques. Experience with coverage-driven verification (CDV) methodologies. * Prior experience with performance verification and bottleneck analysis.