Job Description

Project Role :

Digital Design Engineer

Project Role Description :

Design and implement digital circuits and systems, focusing on logic, timing, and power optimization. Write RTL code, simulate, and verify designs to ensure functionality meets performance requirements. Collaborate with physical design, verification, and software teams to integrate and validate the design in the overall system.

Must have skills :

RTL Design

Good to have skills :

NA

Minimum

7.5

year(s) of experience is required

Educational Qualification :

15 years full time education



Summary: Role Overview: We are looking for a highly motivated Senior RTL Design Engineer to join our SoC/ASIC/FPGA development team. The role involves end-to-end RTL design, integration, and optimization of complex digital blocks, ensuring high-quality, reusable, and scalable designs. The candidate will work closely with architecture, verification, physical design, and validation teams. Location:- Bangalore Key Responsibilities: o Own specification, micro-architecture, and RTL implementation of digital IP/SoC subsystems. o Write synthesizable RTL code (SystemVerilog/Verilog/VHDL) and ensure design quality through lint, CDC, and synthesis checks. o Collaborate with architects to understand design requirements and translate them into efficient micro-architectures. o Drive block-level and subsystem-level integration into SoC. o Work with verification teams to review test plans, support debug, and close coverage. o Perform timing analysis and design optimization to meet performance, power, and area goals. o Contribute to design reviews, coding guidelines, and best practices. o Should have prior experience on protocols like AXI/PCI/NOCs/PCIe. o Encryption algorithm is an added advantage. o Collaboration with Verification team and PD team and DFT team o Perform design optimization. o UPF/VCLP/LEC/ ECOs




15 years full time education