Job Description

Overview:

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences--from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges--striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

Responsibilities:

SE

NIOR

SILICON DESIGN ENGINEER

:

DFX Timing

THE ROLE:

As a member of the G&E SoC DFT Team, the successful candidate will own the DFT timing responsibilities for the next gen of AMD SoCs.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

The candidate must have thorough knowledge of timing concepts and also have an undersatnding of DFT basics such as scan insertion, fault models, ATPG on-chip compression techniques that reduce test time and tester memory.



Proficiency in timing constraints and timing closure. Expertise in STA tools Strong understanding of advanced STA concepts and challenges in advanced nodes Thorough knowledge of timing closure flow and methodology Proficiency scripting languages (TCL, Perl, Python) Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team

PREFERRED EXPERIENCE:

Experience in DFT implementation Experience in Test STA Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Proficient in logic design using Verilog Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills.

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer


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Qualifications:
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.