Dft Lead ( Mts Level )
Job Description
Responsibilities include: Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT RTL at the SoC level Working closely with the ATPG team for coverage support, with the DV team on helping debugging and root-causing the test failures and with the PD team on DFT timing closure. Requirements: Experience in DFT architecture for complex chips Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration Proficient in doing basic unit-level verification using simulations . Experience with RTL quality check tools/methodologies such as Spyglass , CDC, Lint is required. Must have experience with integration of various IPs into complex SOCs. Exposure to Static timing analysis Timing closure is required. Any prior experience with microprocessor designs is a plus. Excellent hands-on debug skills and scripting skills are critical. Must have good communication skills and the ability to work in a worldwide team environment. Knowledge experience of low power concepts, clock gating, power gating is a plus Experience with post-silicon bring up is a plus Qualifications: B.E/B.Tech/M.E/M.Tech in Electrical/Electronic s Engineering 7+ years experience in RTL design
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Job Detail
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Job IdJD3163882
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationBangalore, Karnataka, India
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EducationNot mentioned
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ExperienceYear