Job Description

About us:



Tessolve Semiconductors,

a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions.

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 3500+ employees worldwide,

Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.

Tessolve

offers a highly competitive compensation and benefits along with an electric work environment to scale one's intellect, skills and growth.

Position: Sr. Design Lead- DFT



Experience: 6+ relevant experience.



Location - India



To be successful in this role you will:



Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Design for Test skills and Tools .

Technical Skillset Required:



Define and implement DFT architecture and strategy for complex SoCs and ASICs

Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures

Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows

Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met

Debug DFT-related issues during simulation, emulation, and silicon bring-up

Perform timing analysis and constraints development for DFT logic

Drive silicon validation and yield improvement initiatives related to DFT

Document DFT design and verification methodology

Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation

Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.)

Good understanding of RTL design, synthesis, and timing closure

Knowledge of safety-critical or automotive DFT requirements

Familiarity with scripting (Perl, Python, Tcl) for automation

Excellent problem-solving and debugging skills

Strong communication and teamwork abilities

Job Types: Full-time, Permanent

Pay: ?300,000.00 - ?5,000,000.00 per year

Benefits:

Cell phone reimbursement Food provided Health insurance Paid sick time Paid time off Provident Fund Work from home
Schedule:

Day shift Monday to Friday
Supplemental Pay:

Joining bonus Performance bonus Yearly bonus
Work Location: In person

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Job Detail

  • Job Id
    JD3904816
  • Industry
    Not mentioned
  • Total Positions
    1
  • Job Type:
    Full Time
  • Salary:
    Not mentioned
  • Employment Status
    Permanent
  • Job Location
    KA, IN, India
  • Education
    Not mentioned
  • Experience
    Year