Job Description

Title: Design for Testability (DFT)
Location: Bangaluru,Chennai
Exp: Minimum 3 year(s) of experience
:
Roles & Responsibilities:
Bachelor's degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.

• Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs
• Core DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug
• Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)o Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl
• Proficient in Unix/Linux environments
• Strong fundamentals in Digital Circuit Design and Logic Design are required.

Professional & Technical Skills:- Must To Have Skills: Proficiency in Design for Testability (DFT)
- Strong understanding of software development methodologies
- Experience in leading and managing software development projects
- Knowledge of technologies and tools used in software development
- Excellent communication and interpersonal skills