Job Description

Job Overview
We are looking for DFT-trained fresh graduates who are passionate about VLSI and semiconductor design. This role is ideal for candidates who have completed professional VLSI/DFT training from reputed institutes such as Maven or similar and are eager to begin their career in Design for Test (DFT) for advanced ASIC/SoC projects.
Selected candidates will work closely with experienced DFT and design teams, gaining exposure to real-time chip development flows, testing methodologies, and industry-standard tools. Eligibility Criteria
B.Tech in ECE / EEE / E&I or related streams
Year of Passing: 2023/2024 or earlier
Completed DFT/VLSI training from recognized institutes (Maven or equivalent)
Strong interest in Semiconductor & VLSI domain Key Responsibilities
Support DFT engineers in scan insertion, scan chain validation, and ATPG activities
Assist in MBIST and boundary scan implementation tasks
Participate in fault analysis and basic debugging activities
Work on test pattern generation and validation under guidance
Contribute to improving DFT flows and documentation
Collaborate with design and verification teams for issue resolution Required Technical Skills
Strong fundamentals in Digital Electronics and VLSI concepts
Basic understanding of DFT methodologies:
Scan insertion & Scan chain concepts
ATPG basics
MBIST fundamentals
Boundary Scan concepts
Knowledge of fault models (stuck-at, transition faults)
Basic exposure to industry DFT tools (training-level exposure acceptable)
Working knowledge of Verilog HDL
Good analytical thinking and debugging skills Soft Skills
Good communication and teamwork abilities
Strong learning attitude and problem-solving mindset
Passion for building a career in VLSI/DFT Nice to Have
Hands-on lab/project work during VLSI training
Basic scripting knowledge (TCL/Python)
Understanding of ASIC design flow
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Skills Required